OSPI Baud Rate Select Register
| SCKDV | OSPI Clock Divider. This field contains the MSB 15 bits of the 16-bit SPI_CLK divider value. The LSB for this bit field is always set to 0 and is unaffected by a write operation, which ensures the divider is always set to an even value. If this field is set to all 0s, the serial output clock (OSPI_SCLK) is disabled. The frequency of the OSPI_SCLK is derived from the following equation: FOSPI_SCLK = FOSPI_CLK/BAUDR Where BAUDR is any even value between 2 and 65534, and BAUDR = SCKDV x 2. For example, for FOSPI_CLK = 3.6864 MHz and SCKDV = 1b’1: BAUDR = 2 and FOSPI_SCLK = 3.6864/2 = 1.8432 MHz |